Platforms (e.g., server platforms) require a performance/power loadline from input/output (I/O) devices, where power consumption is expected to reduce at lower bandwidth utilization. Peripheral component interconnect express (PCIe) devices include lower power states for the platform to utilize during periods of low performance. However, observations of actual server workload characterization show that PCIe link power states (e.g., L0, L1) offer less than ideal power savings as a function of utilization. For example, the L1 state offers power savings at or near OS Idle, but the link is predominantly active—even at very low bandwidth utilization (e.g., <5%). Owing to the nature of I/O traffic (e.g., server I/O traffic), timeout based link power management states have very low residency. Thus, such states exist but they are not adequately utilized.
Consequently, I/O power is inefficiently utilized at the component level and at the platform level (e.g., inappropriate fan speed and corresponding current draw). There are also resulting thermal inefficiencies due to a lack of adequate thermal throttling in the event of thermal excursions.